The Df T-Architect coordinates across IC architecture, Df T, Design and Test & Product engineering disciplines. He/she is responsible for the Analog and overall Df T Architecture and proper implementation in the design. Overall goal is to aim for an optimal industrial test concept and an appropriate Df T realization according to the required test cost vs. product quality balance within the project determined constraints. His/her focus is on complex AMS-SOC projects (50% analog / 50% digital). The Df T-Architect is the technical lead of the Df T-implementation team and advises analog and digital IP designers and software engineers. Your job Primary Accountabilities: Advises the system/hardware architect on testability provisions in the IC/IP architecture to enable high test coverage and easy test access. Responsible for the testability requirements of the IC/IP and its composing modules. Responsible for test case definition. Responsible for identifying test impact of requirement changes. Specifies chip level test concepts requirements (e.g., integrated test modules in digital and analogue IP’s, test access and control blocks, build-in self-test circuitries, etc.). Defines test strategy and Df T architecture to achieve the specified quality level for lowest integral test cost. Develops a test architecture which enables fast failure analysis and debug capability on IC/IP level. Aims for cost effectiveness and maximum reusability of test functionality and concepts. Supports predictions on factory yields, fall-off rate, delivery quality, test coverage, test cycle time, and test costs. Defines test-circuits and structures in IC/IP, analyzes and verifies the testability and test coverage in IC/IP. In larger projects, he usually guides the Df T-implementation team and assists appropriate digital and analog designers in charge to implement special Df T circuitry. Involved in the test verification and validation process of the product, to support this with test tools and to verify the anticipated fault models on relevance and completeness for usage in a Df T- and test verification context. Supports and consults design team members on test-related issues, as well as coaches test- and product engineers in the area of Design-for-Testability. Assists other team members to generate fully verified test patterns and test methods. Aids the test engineering during test program development and debug. Candidate profile:5-10 years experience in Semiconductor. M. Sc. degree in Electronic Engineering or similar. Experience with analog design. Familiar with Design-for-Test for mixed signal Df T methods. Good understanding of fault models (including analog), ATPG, scan insertion and compression techniques, BIST, and IJTAG. Experience with logic design (System Verilog and VHDL), ASIC design flow, clocking, and reset methods. Open proactive communicator, enjoys interactive and iterative development process. Rigorous in documentation. Willing to challenge and improve design methodologies. Experience with EDA tools. Desirable: Logical synthesis and static timing analysis. Fluent in English. Please note: The successful candidate may/will be responsible for security related tasks. The assignment may/will be in scope of security certifications, therefore a conscious and reliable way of working is necessary.
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